This invention relates to a data processing apparatus which performs image processing at high speed, for example, a G4 facsimile apparatus.
An image processing apparatus which must perform image processing at high speed, for example, a G4 facsimile apparatus, has conventionally adopted a construction in which an image bus dedicated to image processing is separated from a main CPU bus connected to a main CPU for controlling the entire apparatus.
FIG. 3 shows an example of the construction of a conventional G4 facsimile apparatus.
A main CPU 301 controls the operation of the entire facsimile apparatus, and is connected to a main CPU bus 3a. Connected to this main CPU bus are a ROM 302 for scoring instruction programs on the operations to be performed by the main CPU 301, a RAM 303 for storing operation data, a communication-control-circuit DMAC (direct memory access controller) 304, a communication control circuit 305, and an image memory 306. The communication control circuit 305 performs transmission and reception of data with a terminal at the other end of a line 3c. After performing communication processes by a predetermined procedure, the communication control circuit 305 utilizes the communication-control-circuit DMAC 304 to write the received data to an image memory or, conversely, to read image data for transmission from the image memory and transmit the same to the line.
A local CPU 307 mainly controls image processing. By using a part of the image memory 306, the local CPU 307 can perform an inter-CPU communication with the main CPU 301, giving and receiving commands to and from each other. The local CPU 307 operates to execute processes as demanded by the main CPU 301. A local ROM 308 and a local RAM 309 are used for the operations of the local CPU 307. Their functions in connection with the local CPU 307 are the same as those of the main ROM 302 and the main RAM 303 in connection with the main CPU 301.
A DMAC 310 performs image data transfer between the image memory 306 and an image processing circuit 311, or between the image memory 306 and a printer interface circuit 312, or between the image memory 306 and a scanner interface circuit 313. To effect this image transfer, the local CPU gives a command to the DMAC 310 in accordance with a command from the main CPU. Through the above processes, image data received from the line is image-processed through the image memory 306 and supplied to a printer 314, or image data received from a scanner 315 is image-processed and transmitted to the line via the image memory 306 and the communication control circuit 305.
A problem with the above conventional system is that it requires a plurality of CPUs, i.e., main and local CPUs. Further, to operate these CPUs, it is necessary to provide a plurality of peripheral circuits each including ROM, RAM, etc. Thus, the system requires a complicated circuit configuration and is rather expensive.
Further, since a plurality of CPUs perform communication through a memory, each CPU requires an inter-CPU communication program of its own, the commands being given to an image processing circuit, a DMAC, etc. through these programs, with the result that command transmission takes a long time.
In addition, commands from the local CPU are given to a DMAC, an image processing circuit, etc. through an image bus, so that the image bus is occupied by the local CPU for the while, thereby deteriorating the image data transfer efficiency.